Bulk silicon field effect transistors (FETs) are formed on the surface of a silicon chip or wafer. In what is typically referred to as CMOS technology, the silicon wafer or substrate may be of one conduction type, e.g., P-type, and areas or wells of a second conduction type, e.g., N-type, are formed in the P-type wafer. N-type FETs (NFETs) are formed on the surface of the P-type wafer and P-type FETs (PFETs) are formed on the surface of the N-wells. FET device characteristics, including threshold voltage (Vt) and device currents, are dependent upon device substrate voltage (Vsx). So, typically, a first bias voltage, typically zero Volts (0V) or ground (GND), is applied to the substrate to bias the NFETs and a second bias voltage, typically the supply voltage (Vdd or Vhi), is applied to the N-wells. The substrate and N-well bias (or, collectively, back bias) voltages help to stabilize respective FET electrical characteristics, including improving Vt and device current stability. Changing a device bias conditions changes device characteristics; increasing/decreasing device Vt and decreasing/increasing device operating current depending upon the magnitude and direction of the respective change.
Performance improvements for these prior art bulk transistor technologies has been achieved, primarily, by reducing feature size or “scaling.” More recently, silicon on insulator (SOI) technology has become the main source of performance improvement for transistors. SOI transistors may be formed on the surface of a silicon layer isolated from a silicon substrate by a buried oxide (BOX) layer. In a typically complex series of mask steps, shallow trenches filled with oxide isolate SOI islands of the surface silicon layer on which FETs are formed. Circuit wiring in layers above the FETs connects the FETs into circuits. The state of the art, partially depleted (PD) SOI technology includes a semiconductor layer thick enough that, the FET channel region does not fully deplete through its full thickness when the device is off. The advantage of the PD SOI structure is that device operation and design are very close to bulk CMOS.
Ideally, each FET is isolated from unintended parasitic effects from every other FET. Back biases may be applied to SOI FETs through a contact to the underlying layer (or body contact) that may require as much area as the FET itself and may make circuit wiring more difficult. Consequently, especially for dense SOI memory arrays, body contacts are omitted completely for maximum device density. Unfortunately, as body contacts are eliminated or at the very least shared by more and more devices, individual devices become much more susceptible to localized device phenomena known as body effects. Localized body effect variations cause device non-uniformity.
Body effects, also known as history effects, occur in completely or partially isolated devices, especially in analog logic circuit FETs, memory devices (FETs) or in logic where device body contacts may be infrequent or eliminated. As a particular device switches off, charge (i.e., majority carriers) remains in the device body beneath the channel. Device leakage and parasitic bipolar effects may add to the charge. Charge builds at isolated locations as the chip operates because the charge from fast switching devices is injected into locally isolated body pockets faster than it dissipates. Eventually, the injected charge reaches some steady state value that acts as a substrate bias for the device. This steady state change depends upon each particular device's switching history and is typically known as the history effect for the particular device. So, body effects may cause two devices that are identical by design may exhibit some difference, difference that may be time varying from changing circuit conditions. Normally, slight variations in device characteristics such as device thresholds, are negligible, neglectable and not given much consideration for typical logic circuits such as decoders, clock buffers, input or output drivers and array output drivers.
These localized body effects and other sporadically occurring parasitic bipolar effects, i.e., at source/drain diffusion junctions, are serious design problems for densely packed SOI circuits such as for example, memory arrays, e.g., a Static RAM (SRAM) macro. A SRAM cell is, essentially, an identical pair of cross coupled transistors loaded with high resistance load resistors and a pair of pass transistors between internal storage nodes and a pair of bit lines. The state of the cross coupled pair determines the state of data stored in the cell. Each SRAM cell is read by coupling the cross coupled transistors through the access transistors to the bit line pair and measuring the resulting voltage difference on the bit line pair. The signal on the bit line pair increases with time toward a final state wherein each one of the pair may be, ultimately, a full up level and a full down level. However, to improve performance, the voltage difference is sensed well before the difference reaches its ultimate value.
Thus, the channel bias of any device is dependent upon its current operating state and the device's history, i.e., any previously introduced remaining charge. Charge in any particular device may vary as the chip operates because individual devices switch somewhat independently of each other. As noted above, FET device characteristics are dependent upon device substrate voltage. For typical individual logic circuits such as, decoders, clock buffers, input or output drivers and array output drivers, device characteristics variations that result from floating device channels, may be negligible, neglectable and given little consideration.
However, repetitively accessing RAM cells, both to read and to write, unintentionally induces local body effects in some cell devices. These body effects change cell device thresholds and modulate device currents for affected devices, reducing the signal stored in the cell as well as the signal passed by cell access transistors. These local effects can cause the SRAM cell to favor one state over the other, resulting in sporadic read upsets with no apparent reason. An imbalance in cell pass gates may increase cell write time and sense time. As a result, intermittent problems may arise, such as spuriously reading the wrong data or, random cell failures. These types of intermittent problems are notoriously difficult to identify and diagnose. So, channel bias variations from body effects causes device non-uniformities that result in difficult to identify sporadic chip failures sometimes characterized as “soft failures.”
Dynamic circuits are Especially sensitive to such process variations which can result in inter or intra macro timing problems, race conditions, high leakage/power and reduced noise margins. In analog circuits (e.g., SRAM sense amplifiers) device body voltages can drift from cycle to cycle. Consequently, such chips, macros and other circuits with threshold variation sensitivities, either have performance and reliability below what it might be with back biased devices or, are larger (and so, more expensive) than they might otherwise be if body contacts were not included.
Thus, there is a need for a improved SOI device stability and especially for SRAM devices.